The 21256 is a 256K * 1 DRAM t

The 21256 is a 256K * 1 DRAM that consists of a 512 * 512 array of cells. The cells must be refreshed within 4 ms for data to be retained. Each time a CAS before RAS refresh cycle occurs, the on-chip refresh circuitry will refresh a row of the array at the row address specified by a refresh counter. The counter is incremented after each refresh. How often should CAS-before- RAS cycles be applied in order for all of the data to be retained?

 

The SDRAM on the DE1 board from Terasic contains an 8 Mbyte SDRAM. This IC has 12 address 1A11-A02. All 12 address bits are latched into the row address register by RAS. The IC has two input pins (separate from the address inputs) to specify which bank is being accessed.

(a) How many banks are in this IC?

(b) How many bytes are in each bank?

(c) How many rows must be refreshed on this SDRAM?

(d) How many bits must be latched into the column address register to select one of the memory bytes stored in the selected bank?

 

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